1. Field of the Invention
The present invention relates to a semiconductor apparatus having a monitor circuit for perceiving critical path delay characteristics of a target circuit, and particularly relates to a technique of attaining a low power consumption by adaptively controlling a power source voltage supplied to an LSI as the target circuit.
2. Description of the Related Art
In recent years, a method of lowering a power source voltage for attaining a low power consumption has been generally used in a semiconductor circuit. This is because AC components of a power consumption of a semiconductor circuit (LSI) is proportional to a square of a power source voltage, and a reduction of the power source voltage is the most effective for lowering a power consumption of the LSI.
From such a viewpoint, in recent years, there has been reported a method for adaptively supplying a minimum voltage for operating an LSI by dynamically controlling a power source voltage against unevenness of an operation frequency and a process of the LSI and temperature changes.
In an example of realizing control of the above adaptive power source voltage, a delay circuit for generating delay corresponding to a critical path of an LSI is installed, and an operation clock frequency of a target circuit as an object of the power source controlling is compared with a delay value of the delay circuit, and the power source voltage is controlled so that the delay value of the delay circuit falls into an operation clock cycle (for example, refer to the Japanese Unexamined (Kokai) Patent Publication No. 2000-216338, No. 2000-295084 and No. 2002-100967).
Also, the critical path of the LSI is switched due to changes of the operation voltage and process in some cases.
To deal with the switching of the critical path as such, there has been proposed a method for installing a plurality of delay circuits and selecting one having the largest delay among delay values of the all delay circuits in order to control the power source voltage.
However, installation of a large number of delay circuits for dealing with the path switching leads to an increase of the circuit scale, and trade-off imbalance arises between delay monitoring accuracy and the circuit scale due to the delay circuits.